Plasma etching devices are commonly employed during one or, more of the phases of the integrated circuit fabrication process, and are typically available in either a single-wafer or a plural-wafer configuration. The single-wafer configurations, while providing excellent process control, suffer from a restricted system throughout capability. Efforst to relieve the throughput limitations, have been generally unsuccessful. For these high-temperature etching processes, system utility is limited due to the undesirable phenomenon of resist "popping", notwithstanding that various cooling approaches have been used including clamping, cooling of the wafer underside with a helium flow, and the mixing of helium into the plasma. The multiple-wafer configurations, while providing a comparatively much-greater system throughput, have been generally subject to less-than-desirable process and quality control. Not only are end-point determinations for each of the multiple wafers either not available or not precisely determinable, but also electrode positional accuracy for different electrode gaps and. correspondingly different gas chemistries is often difficult to establish and maintain. The single-wafer and the multiple-wafer configurations are both subject to the further disadvantage that two or more step processes typically expose the wafers to an undesirable environment in the intermediate handling step, which materially increases the possibility of wafer contamination, and which further restricts the processing throughput.